A low drop-out DC voltage regulator is a regulator circuit that provides a controlled and stable DC voltage relative to a reference voltage. The operation of the circuit is based on feeding back an amplified error signal which is used to control output current flow of a pass device, such as a power field-effect transistor (‘FET’) driving a load. The drop-out voltage is the difference between the supply voltage and the output voltage below which regulation is lost. The minimum voltage drop required across the LDO regulator to maintain regulation is just the voltage across the pass device.
The low drop-out nature of the regulator makes it appropriate (over other types of regulators such as DC-DC converters and switching regulators) for use in many applications such as automotive, portable, and industrial applications. In the automotive industry, the low drop-out voltage is necessary for example during cold-crank conditions where an automobile's battery voltage can be below 6V. LDO voltage regulators are also widely used in mobile products with battery power supplies (such as cellular phones, personal digital assistants, cameras and laptop computers), where the LDO voltage regulator typically needs to regulate under low supply voltage conditions.
The main components of a simple LDO DC linear voltage regulator are a power amplifier such as an FET forming the pass device and a differential amplifier (error amplifier). One input of the differential amplifier monitors a percentage of the output, as determined for example by the ratio of a resistive voltage divider across the output. The second input to the differential amplifier is from a stable voltage reference (such as a bandgap reference voltage source). If the output voltage rises too high relative to the reference voltage, the drive to the power FET changes so as to maintain a constant output voltage. These elements constitute a DC regulation loop which provides voltage regulation.
In a typical LDO voltage regulator, the first stage (the error amplifier) presents a high impedance node. This high impedance node creates a frequency pole. The power amplifier, the output (including the load) and the first stage pole would give instability, which is avoided by using the output pole as the dominant pole to get stability. Generally this type of driver is still unstable when the load capacitance is 0. Accordingly, the output capacitance has to be specified, as does a minimum and maximum Equivalent Series Resistance (‘ESR’). As the load is part of the regulation loop, it is still possible for instability to be caused by such indeterminate factors as parasitic capacitance.
U.S. Pat. No. 6,373,233 describes a LDO voltage regulator including a capacitor connected in a compensation circuit element between control and output terminals of an output transistor. The voltage characteristics of the capacitor must be compatible with the usage specification and for a high voltage application, such as a 40 volt maximum output voltage, for example, the capacitor cannot be integrated in the manufacturing process of the voltage regulator using some metal-oxide-Silicon manufacturing techniques.
Transient load regulation is another important parameter of a LDO voltage regulator but U.S. Pat. No. 6,373,233 gives no information on how adequate performance in this respect could be achieved.